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features ? dual marked with device part number and dla drawing number ? manufactured and tested on a mil-prf-38534 certifi ed line ? qml-38534, class h and k ? five hermetically sealed package confi gurations ? performance guaranteed over full military temperature range: -55c to +125c ? high speed: 10 mbd typical ? cmr: > 10,000 v/s typical ? 1500 vdc withstand test voltage ? 2500 vdc withstand test voltage for hcpl-565x ? high radiation immunity ? 6n137, hcpl-2601, hcpl-2630/31 function compatibility ? reliability data ? ttl circuit compatibility applications ? military and aerospace ? high reliability systems ? transportation, medical, and life critical systems ? line receiver ? voltage level shifting ? isolated input line receiver ? isolated output line driver ? logic ground isolation ? harsh industrial environments ? isolation for computer, communication, and test equipment systems caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. the connection of a 0.1 f bypass capacitor between v cc and gnd is recommended. 6n134,* 81028, hcpl-563x, hcpl-663x, hcpl-565x, 5962-98001, hcpl-268k, hcpl-665x, 5962-90855, hcpl-560x hermetically sealed, high speed, high cmr, logic gate optocouplers data sheet *see matrix for available extensions. description these units are single, dual and quad channel, hermeti- cally sealed optocouplers. the products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full mil-prf-38534 class level h or k testing or from the appropri ate dla drawing. all devices are man- ufactured and tested on a mil-prf-38534 certifi ed line and are included in the dla quali fi ed manufacturers list qml-38534 for hybrid microcircuits. quad channel devices are available by special order in the 16 pin dip through hole packages. functional diagram v cc v out v e gnd truth table (positive logic) multichannel devices input output on (h) l off (l) h single channel dip input enable output on (h) h l off (l) h h on (h) l h off (l) l h multiple channel devices available
2 each channel contains a gaasp light emitting diode which is optically coupled to an integrated high speed photon detector. the output of the detector is an open collector schottky clamped transistor. internal shields pro vide a guaranteed common mode transient immuni- ty specifi cation of 1000 v/s. for isolation voltage appli- cations requiring up to 2500 vdc, the hcpl-5650 family is also available. package styles for these parts are 8 and 16 pin dip through hole (case outlines p and e respectively), and 16 pin surface mount dip fl at pack (case outline f), leadless ceramic chip carrier (case outline 2). devices may be purchased with a variety of lead bend and plat- ing options. see selection guide table for details. stan- dard microcircuit drawing (smd) parts are available for each package and lead style. because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifi cations, and per- formance characteristics shown in the fi gures are iden- tical for all parts. occasional exceptions exist due to package variations and limitations, and are as noted. additionally, the same package assembly processes and materials are used in all devices. these similarities give justifi cation for the use of data obtained from one part to represent other parts performance for reliability and certain limited radiation test results. selection guideCpackage styles and lead confi guration options package 16 pin dip 8 pin dip 8 pin dip 8 pin dip 16 pin flat pack 20 pad lccc lead style through hole through hole through hole through hole unformed leads surface mount channels 2 1 2 2 4 2 common channel wiring v cc , gnd none v cc , gnd v cc , gnd v cc , gnd none withstand test voltage 1500 vdc 1500 vdc 1500 vdc 2500 vdc 1500 vdc 1500 vdc avago part # & options commercial 6n134 [1] hcpl-5600 hcpl-5630 hcpl-5650 hcpl-6650 hcpl-6630 mil-prf-38534, class h 6n134/883b hcpl-5601 hcpl-5631 hcpl-5651 hcpl-6651 hcpl-6631 mil-prf-38534, class k hcpl-268k hcpl-560k hcpl-563k hcpl-665k hcpl-663k standard lead finish gold plate gold plate gold plate gold plate gold plate solder pads* solder dipped* option #200 option #200 option #200 option #200 butt cut/gold plate option #100 option #100 option #100 gull wing/soldered* option #300 option #300 option #300 class h smd part # prescript for all below none 5962- none none none none gold plate 8102801ec 9085501hpc 8102802pc 8102805pc 8102804fc solder dipped* 8102801ea 9085501hpa 8102802pa 8102805pa 81028032a butt cut/gold plate 8102801uc 9085501hyc 8102802yc butt cut/soldered* 8102801ua 9085501hya 8102802ya gull wing/soldered* 8102801ta 9085501hxa 8102802za class k smd part # prescript for all below 5962- 5962- 5962- 5962- 5962- gold plate 9800101kec 9085501kpc 9800102kpc 9800104kfc solder dipped* 9800101kea 9085501kpa 9800102kpa 9800103k2a butt cut/gold plate 9800101kuc 9085501kyc 9800102kyc butt cut/soldered* 9800101kua 9085501kya 9800102kya gull wing/soldered* 9800101kta 9085501kxa 9800102kza *solder contains lead. note: 1. jedec registered part.
3 outline drawings 16 pin dip through hole, 2 channels functional diagrams 16 pin dip 8 pin dip 8 pin dip 16 pin flat pack 20 pad lccc through hole through hole through hole unformed leads surface mount 2 channels 1 channel 2 channels 4 channels 2 channels note: all dip and fl at pack devices have common v cc and ground. single channel dip has an enable pin 7. lccc (leadless ceramic chip carrier) package has isolated channels with separate v cc and ground connections. all diagrams are top view. leaded device marking leadless device marking 0.20 (0.008) 0.33 (0.013) 4.45 (0.175) max. 20.06 (0.790) 20.83 (0.820) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.89 (0.035) 1.65 (0.065) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) note: dimensions in millimeters (inches). 3.81 (0.150) min. gnd 1 v o2 19 20 2 3 v o1 8 7 v cc2 v cc1 10 gnd 2 15 13 12 5 7 6 8 12 10 11 9 gnd 1 3 2 4 16 14 15 13 v cc v o1 v o2 v cc v out v e gnd 1 2 3 4 5 7 6 8 12 10 11 9 gnd 1 3 2 4 16 14 15 13 v cc v o1 v o3 v o2 v o4 1 3 2 4 8 6 7 5 v cc gnd v o2 v o1 8 7 6 5 notes 1. qualifi ed parts only compliance indicator, [1] date code, suffix (if needed) a qyywwz xxxxxx xxxxxxx xxx xxx * 50434 country of mfr. avago cage code [1] avago logo dla smd [1] pin one/ esd ident avago p/n dla smd [1] * qualified parts only compliance indicator, [1] date code, suffix (if needed) a qyywwz xxxxxx * xxxx xxxxxx xxx 50434 dla smd [1] avago cage code [1] avago logo country of mfr. avago p/n pin one/ esd ident dla smd [1] * qualified parts only
4 outline drawings (continued) 16 pin flat pack, 4 channels 8 pin dip through hole, 2 channels 2500 vdc withstand test voltage 20 terminal lccc surface mount, 2 channels 8 pin dip through hole, 1 and 2 channels 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches). 3.81 (0.150) min. 5.08 (0.200) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches). 8.13 (0.320) max. 5.23 (0.206) max. 2.29 (0.090) max. 7.24 (0.285) 6.99 (0.275) 1.27 (0.050) ref. 0.46 (0.018) 0.36 (0.014) 11.13 (0.438) 10.72 (0.422) 2.85 (0.112) max. 0.89 (0.035) 0.69 (0.027) 0.31 (0.012) 0.23 (0.009) 0.88 (0.0345) min. 9.02 (0.355) 8.76 (0.345) note: dimensions in millimeters (inches). 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 plcs) 4.95 (0.195) 5.21 (0.205) 8.70 (0.342) 9.10 (0.358) 1.78 (0.070) 2.03 (0.080) 0.51 (0.020) 0.64 (0.025) (20 plcs) 1.52 (0.060) 2.03 (0.080) metallized castillations (20 plcs) 2.16 (0.085) terminal 1 identifier note: dimensions in millimeters (inches). solder thickness 0.127 (0.005) max. 1.14 (0.045) 1.40 (0.055)
5 hermetic optocoupler options option description 100 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this option is available on commercial and hi-rel product in 8 and 16 pin dip (see drawings below for details). 200 lead fi nish is solder dipped rather than gold plated. this option is available on commercial and hi-rel prod- uct in 8 and 16 pin dip. dla drawing part numbers contain provisions for lead fi nish. all leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. 300 surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. this option is avail- able on commercial and hi-rel product in 8 and 16 pin dip (see drawings below for details). this option has solder dipped leads. solder contains lead. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5 max. 4.57 (0.180) max. 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 1.07 (0.042) 1.32 (0.052)
6 absolute maximum ratings no derating required up to +125c. parameter symbol min. max. units storage temperature t s -65 +150 c operating temperature t a -55 +125 c case temperature t c +170 c junction temperature t j +175 c lead solder temperature 260 for 10 sec c peak forward input current (each channel, 1 ms duration) i f(peak) 40 ma average input forward current (each channel) i f(avg) 20 ma input power dissipation (each channel) 35 mw reverse input voltage (each channel v r 5v supply voltage (1 minute maximum) v cc 7.0 v output current (each channel) i o 25 ma output voltage (each channel) v o 7* v output power dissipation (each channel) p o 40 mw package power dissipation (each channel) p d 200 mw *selection for higher output voltages up to 20 v is available single channel product only enable input voltage v e 5.5 v note enable pin 7. an external 0.01 f to 0.1 f bypass capacitor must be connected between v cc and ground for each package type. 8 pin ceramic dip single channel schematic esd classifi cation (mil-std-883, method 3015) hcpl-5600/01/0k ( ? ), class 1 6n134, 6n134/883b, hcpl-5630/31/3k, hcpl-5650/51, hcpl-6630/31/3k and hcpl-6650/51/5k (dot), class 3 recommended operating conditions parameter symbol min. max. units input current, low level, each channel i fl 0 250 a input current, high level, each channel* i fh 10 20 ma supply voltage, output v cc 4.5 5.5 v fan out (ttl load) each channel n 6 *meets or exceeds dla smd and jedec requirements.
7 electrical characteristics (t a = -55c to +125c, unless otherwise specifi ed) parameter symbol test conditions group a [13] sub- groups limits units fig. note min. typ.** max. high level output current i oh *v cc = 5.5 v, v o = 5.5 v, i f = 250 a 1, 2, 3 20 250 a 1 1 low level output voltage v ol *v cc = 5.5 v, i f = 10 ma, i ol (sinking) = 10 ma 1, 2, 3 0.3 0.6 v 2 1, 9 current transfer ratio h f ctr v o = 0.6 v, i f = 10 ma, v cc = 5.5 v 1, 2, 3 100 % 1 logic high supply current single channel i cch *v cc = 5.5 v, i f = 0 ma 1, 2, 3 9 14 ma 1 dual channel v cc = 5.5 v, i f1 = i f2 = 0 ma 18 28 ma 6 quad channel v cc = 5.5 v, i f1 = i f2 = i f3 = i f4 = 0 ma 25 42 ma logic low supply current single channel i ccl *v cc = 5.5 v, i f = 20 ma 1, 2, 3 13 18 ma 1 dual channel v cc = 5.5 v, i f1 = i f2 = 20 ma 26 36 ma 6 quad channel v cc = 5.5 v, i f1 = i f2 = i f3 = i f4 = 20 ma 33 50 ma input forward voltage v f *i f = 20 ma 1, 2, 3 1.5 1.9 v 3 1, 15 1, 2 1.55 1.75 v 3 1, 16 3 1.85 input reverse breakdown voltage bv r *i r = 10 a 1, 2, 3 5 v 1 input-output leakage current i i-o * rh 65% t a = 25c t = 5 s v i-o = 1500 vdc 1 1.0 a 2, 8, 17 v i-o = 2500 vdc 1 1.0 a 18 capacitance between input/ output c i-o f = 1 mhz, t c = 25c 4 1.0 4.0 pf 1, 3, 14 *identifi ed test parameters for jedec registered parts. **all typical values are at v cc = 5 v, t a = 25c. recommended operating conditions (contd.) single channel product only [10] parameter symbol min. max. units high level enable voltage v eh 2.0 v cc v low level enable voltage v el 0 0.8 v
8 electrical characteristics, (contd) t a = -55c to +125c unless otherwise specifi ed parameter symbol test conditions group a [13] subgroups limits units fig. note min. typ.** max. propagation delay time to high output level t plh *v cc = 5 v, r l = 510 , c l = 50 pf, i f = 13 ma 9 60 100 ns 4, 5, 6 1, 5 10, 11 140 propagation delay time to low output level t phl * 9 55 100 ns 10, 11 120 output rise time t lh r l = 510 , c l = 50 pf, i f = 13 ma 9, 10, 11 35 90 ns 1 output fall time t hl 35 40 common mode transient immunity at high output level |cm h |v cm = 50 v (peak), v cc = 5 v, v o (min.) = 2 v, r l = 510 , i f = 0 ma 9, 10, 11 1000 >10000 v/s 7 1, 7, 14 common mode transient immunity at low output level |cm l |v cm = 50 v (peak), v cc = 5 v, v o (max.) = 0.8 v, r l = 510 , i f = 10 ma 9, 10, 11 1000 >10000 v/s 7 1, 7, 14 single channel product only low level enable current i el v cc = 5.5 v, v e = 0.5 v 1, 2, 3 -2.0 -1.45 ma high level enable voltage v eh 1, 2, 3 2.0 v 10 low level enable voltage v el 1, 2, 3 0.8 v *identifi ed test parameters for jedec registered part. **all typical values are at v cc = 5 v, t a = 25c. typical characteristics, t a = 25c, v cc = 5 v parameter sym. typ. units test conditions fig. note input capacitance c in 60 pf v f = 0 v, f = 1 mhz 1 input diode temperature coeffi cient v f t a -1.5 mv/c i f = 20 ma 1 resistance (input-output) r i-o 10 12 v i-o = 500 v 2 single channel product only propagation delay time of enable from v eh to v el t elh 35 ns r l = 510 , c l = 50 pf i f = 13 ma, v eh = 3 v, v el = 0v 8, 9 1, 11 propagation delay time of enable from v el to v eh t ehl 35 ns 1, 12 dual and quad channel product only input-input leakage current i i-i 0.5 na relative humidity 65% v i-i = 500 v, t = 5 s 4 resistance (input-input) r i-i 10 12 v i-i = 500 v 4 capacitance (input-input) c i-i 0.55 pf f = 1 mhz 4
9 notes: 1. each channel. 2. all devices are considered two-terminal devices; i i-o is measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 3. measured between each input pair shorted together and all output connections for that channel shorted together. 4. measured between adjacent input pairs shorted together for each multichannel device. 5. t phl propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 v point on the leading edge of the output pulse. the t plh propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 v point on the trailing edge of the output pulse. 6. the hcpl-6630, hcpl-6631, and hcpl-663k dual channel parts function as two independent single channel units. use the single channel parameter limits for each channel. 7. cm l is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (v o < 0.8 v). cm h is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (v o > 2.0 v). 8. this is a momentary withstand test, not an operating condition. 9. it is essential that a bypass capacitor (0.01 to 0.1 f, ceramic) be connected from v cc to ground. total lead length between both ends of this external capacitor and the isolator connections should not exceed 20 mm. 10. no external pull up is required for a high logic state on the enable input. 11. the t elh enable propagation delay is measured from the 1.5 v point on the trailing edge of the enable input pulse to the 1.5 v point on the trailing edge of the output pulse. 12. the t ehl enable propagation delay is measured from the 1.5 v point on the leading edge of the enable input pulse to the 1.5 v point on the leading edge of the output pulse. 13. standard parts receive 100% testing at 25c (subgroups 1 and 9). smd and 883b parts receive 100% testing at 25, 125, and -5 5c (sub- groups 1 and 9, 2 and 10, 3 and 11, respectively). 14. parameters are tested as part of device initial characteriza tion and after design and process changes. parameters are guara nteed to limits specifi ed for all lots not specifi cally tested. 15. not required for 6n134, 6n134/883b, 8102801, hcpl-268k and 5962-9800101 types. 16. required for 6n134, 6n134/883b, 8102801, hcpl-268k and 5962-9800101 types. 17. not required for hcpl-5650, hcpl-5651 and 8102805 types. 18. required for hcpl-5650, hcpl-5651 and 8102805 types only. figure 1. high level output current vs. tempera- ture. figure 2. input-output characteristics. figure 3. input diode forward characteristics.
10 figure 4. test circuit for t phl and t plh .* figure 7. test circuit for common mode transient immunity and typical waveforms. figure 6. propagation delay vs. temperature. figure 5. propagation delay, t phl and t plh vs. pulse input current, i fh . gnd v cc i f 5 v v o d.u.t. rm input monitoring node pulse generator z o = 50 t h = 5 ns c l * r l * c l includes probe and stray wiring capacitance. v o 0.01 f bypass v ff gnd v cc i i v cm 510 +5 v output v o monitoring node +- pulse gen. a b d.u.t. 0.01 f bypass
11 figure 10. operating circuit for burn-in and steady state life tests. figure 8. test circuit for t ehl and t elh . figure 9. enable propagation delay vs. temperature. gnd v cc +5 v d.u.t. i f = 13 ma pulse generator z o = 50 t r = 5 ns c l * r l * c l includes probe and stray wiring capacitance. v e v out output v e monitoring node output v o monitoring node 0.01 f bypass gnd v cc d.u.t.* t a = +125 o c * all channels tested simultaneously. v oc conditions: i f = 20 ma v cc v in +- (each output) (each input) i o = 25 ma 0.01 f 200 5.3 v (each output) +5.5 v +5.5 v 200
mil-prf-38534 class h, class k, and dla smd test program avagos hi-rel opto couplers are in compliance with mil- prf-38534 classes h and k. class h and class k devices are also in compliance with dla drawings 81028, 5962- 90855 and 5962-98001. testing consists of 100% screen ing and quality confor- mance inspection to mil-prf-38534. for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries . data subject to change. copyright ? 2005-2012 avago technologies limited. all rights reserved. obsoletes 5968-9407e av02-1336en - october 2, 2012

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